The invention relates to the field of digital circuit timing and clocking.
When digital signals cross clock domain boundaries they have to be captured and synchronized to match the clocking requirements of the destination circuit. Double-data rate devices are able to transfer data at a rate corresponding to twice their specified clock rate by clocking data on both the rising and falling edges of their clock signal. Many electronic devices interfacing with double-data rate devices, however, include at least a portion adapted to process single- or half-data rate signals. In these devices, data moves at half or a quarter of the rate, respectively, of a double-data rate device. In some instances, moreover, a clock signal used by the double data rate device might have a faster frequency than (e.g. double) that of a destination clock signal used by portions of the destination device that is interfacing with the double data rate device. In any event, the data signals from the double-data rate device must be captured by the destination device and synchronized with a destination clock signal used by at least portions of the destination device.
One known read data path circuit for interfacing with double-data rate devices uses a First In, First Out (“FIFO”) buffer for capturing, transferring, and synchronizing data. In a first step, it divides a double-data rate data stream into two parallel single-data rate streams, one containing data derived from the rising edges and another containing data derived from the falling edges of the source circuit clock signal, respectively. In a second step, the two streams are written in parallel to a FIFO on two inputs. In a third step, data written to the FIFO is read out at half-data rate on four outputs. Thus, the FIFO-based approach accomplishes the re-timing of the transferred data by writing data into the FIFO at single-data rate on two ports and reading data out of the FIFO at half-data rate on four ports.
Although the FIFO-based approach is accurate, the FIFO circuit is expensive in terms of latency. Specifically, the transfer of data from the FIFO input to its output may introduce 5-6 clock cycles of delay. The device will often have to stop processing to wait for the read data to return, therefore the performance of the system can be adversely affected by an increase in memory read latency.